This invention relates generally to Dynamic Random Memories (DRAMs) and more particularly to DRAMs having buried capacitors as the storage element thereof.
As is known in the art, it is frequently desirable to form regions of a semiconductor device below (i.e., buried beneath) the surface of a semiconductor substrate (i.e., body). More particularly, it is frequently desirable to form a first region in a semiconductor substrate beneath a surface of such substrate and aligned with a second region also disposed beneath the surface of the substrate. The formation of this first region is typically performed using a lithographic-etching processes. However, in order to form the first region, the mask used in the lithographic-etching process must be properly aligned with the second region which region is buried and thus not visible from the surface. Imprecise proper mask alignment may result in defects.
For example, in a DRAM cell having a buried trench capacitor coupled to a field effect transistor through a buried strap, or coupling region, it is desirable to form the buried strap in precise alignment with a sidewall of the trench after the trench has been formed and then covered with an insulating material. More particularly, after forming the trench, a dielectric liner (i.e., a node dielectric) is formed on the sidewalls of the trench. The trench is filled with a conductive material, typically doped polycrystalline or amorphous silicon. The filled trench is then recessed. A second dielectric layer is formed over the sidewalls exposed by the recess and over the conductive material in the trench the bottom of the recess. A reactive ion etch (RIE) is used to remove the second dielectric from the bottom of the recess while the portions of the second dielectric material remain on the sidewalls of the recess. The remaining second dielectric material forms a dielectric collar for the DRAM cell. Next, the recess is filled with a conductor, typically doped polycrystalline or amorphous silicon. Thus, the second doped material which is in contact with the first doped material together provide a storage node (i.e., electrode) for the buried capacitor. Next, the second doped silicon material is recessed a second time to expose upper portions of the dielectric collar. This exposed upper portion of the dielectric collar is removed together with exposed portions of the node dielectric layer, to thereby re-expose upper portions of the deep trench formed in the semiconductor substrate. Next, a third silicon material is deposed in the second recess to provide the buried strap.
Subsequently, the active area where the transistor is to be formed is delineated (i.e., defined) in the structure by a shallow trench isolation (STI) region formed in the structure. This STI region is then filled with an oxide to complete the isolation of the active area. This oxide fill involves a thermal cycle, for example, subjecting the structure to a temperature of 1000.degree. C. or higher, for about 2 to 10 minutes. This high thermal cycle causes dopant in the buried strap provided by the doped polycrystalline material to out-diffuse into a portion of the active area where the drain region of the transistor will be formed. Unfortunately, the thermal cycle may result in a larger amount of out-diffusion then desired because of the relatively high temperature and relative long thermal cycle time. Thus, excessive out-diffusion may result. This excessive out-diffusion, together with mask misalignments which may occur in the gate formation, may result in inadequate gate channel length for effective operation of the transistor.
One technique suggested is to form the buried strap subsequently to the STI delineation of the cells. With such suggested technique, however, the region in the semiconductor where the buried strap is to be formed (i.e., a region adjacent to the sidewall of the trench) is covered with the STI oxide. Therefore, when a mask is applied to the surface of the structure with an aperture which is to be placed over the region in the semiconductor where the buried strap is to be formed (i.e., a region adjacent to the sidewall of the trench), because the buried strap region is hidden by the STI oxide, a critical mask alignment step is required in order the etch into the semiconductor substrate at the precise location for the buried strap. That is, the mask must be precisely aligned with the sidewalls of the trench used to provide the trench capacitor and such sidewall is unfortunately, hidden by the STI oxide.
Another example where it is desirable to provide a the first region of a semiconductor substrate disposed beneath a surface of such substrate aligned with the second region after such second region is covered with a covering material is in the formation of a field effect transistor having a buried vertical gate channel region aligned with (i.e., having a predetermined lateral separation from) a vertical sidewall of a trench formed in the semiconductor substrate. In order to electrically isolate the transistor from other transistors formed in the semiconductor substrate the Shallow Trench Isolation (STI) technique described above is used. When it desirable to form the vertical gate channel region subsequent to forming the STI step, covering of the semiconductor substrate with the STI oxide conceals the region in the semiconductor substrate where the vertical trench sidewall is to be etched since it is hidden by the STI oxide. Thus, a critically aligned masking step is required to precisely form the buried vertical sidewall and hence the gate channel.